1. Field of the Invention
The present invention relates to a data processing apparatus and method for handling performance of a cache maintenance operation, and in particular to techniques for handling performance of cache maintenance operations in situations where a hierarchical cache structure is used.
2. Description of the Prior Art
A data processing apparatus will typically include data processing circuitry for performing data processing operations on data. Whilst the data processing circuitry could be arranged to communicate directly with memory to retrieve data to be processed, and to store the output data resulting from performance of the data processing operations, it is commonplace to provide a cache structure between the data processing circuitry and memory, with the cache structure being used to store at least a subset of the data for access by the data processing circuitry. The use of such a cache structure significantly reduces the latency that would otherwise result from the requirement to access memory.
For the purposes of the present invention, such a cache structure can take a variety of forms, for example a data cache used to store data values processed by the processing circuitry, an instruction cache with write capabilities and used to store instruction data identifying instructions for execution by the processing circuitry, a translation lookaside buffer (TLB) used to store page table information used when translating virtual addresses issued by the processing circuit into physical addresses, etc.
To enable a balance to be achieved between area and power consumption overhead, and access speed, it is known to provide hierarchical cache structures incorporating multiple levels of cache. For example, a level one (L1) cache may be provided as a first cache to be accessed when the processing circuitry issues an access request. Such a level one cache may have a relatively small storage capacity, but can be accessed very quickly. If the data is not found within the level one cache, then the access request can be forwarded on to a level two (L2) cache which will typically have a larger storage capacity than the level one cache. Various additional levels may be provided beyond the level two cache if required.
It is known to provide mechanisms for performing cache maintenance operations in respect of a cache. Considering a hierarchical cache structure, such cache maintenance operations may require cache maintenance to be performed in each level of the hierarchical cache structure.
Often, although not exclusively, such hierarchical cache structures are used in multi-processing systems where the data processing circuitry is formed of a plurality of separate processing units. The hierarchical cache structure may then be arranged so that each processing unit has its own separate level one cache. However, at a lower level of the hierarchical cache structure, for example at the level two cache, the cache may be shared amongst the processing units. ARM's Cortex-A9 processor is an example of such a multi-processor system. When performing a cache maintenance operation in association with a level one cache in such a system, if a hit occurs in the level one cache (i.e. the data associated with an address specified by the cache maintenance operation is found within the level one cache), then that data will be evicted from the level one cache, with that evicted data being routed to the level two cache. The handling of such evicted data, and the handling of the cache maintenance operation required in respect of the level two cache, will occur independently to one another. Indeed, since in the Cortex-A9 processor the level two cache is not integrated with the multi-core processor, there are in fact two different interfaces used to handle evictions sent to the shared external level two cache, and cache maintenance operations to be performed in respect of the shared external level two cache.
It is becoming more common to integrate a shared level two cache with a multi-core processor, ARM's Cortex-A7 and Cortex-A15 processors being two such examples which incorporate an integrated level two cache. In such processors, evicted data output from the level one cache as a result of a cache maintenance operation is processed in a serial way with respect to the cache maintenance operation to be performed in respect of the level two cache. As a result, the evicted data resulting from the performance of the cache maintenance operation in respect of the level one cache is forwarded to the level two cache and only when the level two cache has processed that evicted data is the cache maintenance operation forwarded to the level two cache for processing.
It would be desirable to provide an improved mechanism for handling cache maintenance operations requiring cache maintenance to be performed in multiple levels of a hierarchical cache structure.